1. Field of the Invention
The present invention generally relates to semiconductor manufacturing, and more particularly to structural and material processing for complementary metal oxide semiconductor devices.
2. Description of the Related Art
Polysilicon is the standard gate material used for advanced complementary metal oxide semiconductor (CMOS) devices. While the use of polysilicon in CMOS gates is attractive due to wide use in the semiconductor industry, it suffers from several disadvantages. For example, the sheet resistance of polysilicon is high (approximately 150 Ohms/Sq.), which leads to timing delays, and the polysilicon must be encapsulated by wide oxide/nitride spacers to prevent interaction with contacts.
Using metal for the gate, drain and source to lower electrical resistance has previously been disclosed in U.S. Pat. Nos. 6,057,583; 6,165,858; 6,033,963; 6,130,123; and 6,049,114, the complete disclosures of which are herein incorporated by reference. For example, in U.S. Pat. No. 6,057,583, it is disclosed to use a metal gate to connect directly to the gate dielectric, and to use metal(s) to form contacts at the source and drain regions. U.S. Pat. No. 6,165,858 teaches the use of metals to form silicide contacts at the source and drain regions. U.S. Pat. No. 6,049,114 describes a process to make a metal gate directly over the gate dielectric, and uses layers of metal silicide to control the work function and to provide a low resistance gate contact.
However, one complication of using metal as the gate contact material is that the design of the transistor device needs to accommodate the different work functions of metal compared to polysilicon. For example, nickel (Ni), tantalum nitride (TaN), ruthenium oxide (RuO), and molybdenum nitride (MoN) are more compatible with P-type doped polysilicon, and ruthenium (Ru), tantalum (Ta), and tantalum silicon silicide (TaSi2) are more compatible with N-type doped polysilicon with mid-bandgap metals, such as tungsten (W), it is difficult to achieve a small threshold voltage.
Another complication is that a reliable liner is needed to prevent metal diffusion into the silicon and the gate dielectric, leading to device breakage. FIGS. 1 and 2 show typical semiconductor structures, including gate contacts, from U.S. Pat. No. 6,130,123 (FIG. 1) and U.S. Pat. No. 6,057,583 (FIG. 2).
FIG. 1 shows substrate 1100 with the shallow trench isolation structures 1110 after the further processing step of forming the nMOS device 191 and pMOS device 192 utilizing tuned metal gate electrodes 1130 and 190 over an active area or cell region denoted by p-type well 105 and n-type well 115, respectively. The nMOS device 191 includes a metal gate electrode 1130 having a work function corresponding approximately to the work function of the n-type doped silicon, with n-type doped diffusion or junction region 195. Similarly, the pMOS device 192 has a metal gate electrode 190 having a work function corresponding approximately to the work function of p-type doped silicon, with p-typed doped silicon diffusion or junction region 200 formed in the substrate. Isolation spacers 152 of a suitable dielectric are incorporated around the gate electrode 1130 and gate electrode 190 to insulate the individual electrodes of the transistor devices. Finally, FIG. 1 as an example, illustrates the coupling of nMOS transistor device 191 and pMOS transistor device 192 for an inverter.
FIG. 2 illustrates a polysilicon layer deposited over dielectrics 46 and 48, and spacers 44 on a substrate 1120. Isolation regions 22 are formed within the semiconductor substrate 20 to isolate the subsequently-formed transistor from adjacent transistors. Portions of the polysilicon layer are subsequently removed, so that a polysilicon gate conductor 64 is formed. Remaining portions 66 of the polysilicon layer are separated from source/drain regions 160 by spacers 44.
One common feature in the conventional devices is that they all employ at least one set of sidewall spacers made of insulator material surrounding the metal gate. In U.S. Pat. No. 6,049,114, the spacers enable the introduction of a gradient of dopants in the source and drain region by ion implantation. In U.S. Pat. Nos. 6,130,123 and 6,057,583, the spacers are used to insulate the metal gate from the source and drain regions of the transistor. Furthermore, anisotropic etching processes are used to form the spacers. In U.S. Pat. Nos. 6,057,583 and 6,033,963 sacrificial/dummy structures are first formed and anchored, and then the sidewall spacers are formed and defined. These sacrificial structures are removed later and replaced as the source/drain and gate structures respectively in these two conventional devices.